Method for forming a double embossing structure

ABSTRACT

A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

This application claims priority to U.S. provisional application No. 60/701,849, filed on Jul. 22, 2005, which is herein incorporated by reference in its entirety.

BACKGROUND OF THE PRESENT INVENTION

1. Field of Invention

The invention relates to a process with a seed layer for two steps of electroplating and the corresponding structure, and more particularly to a metal layer deposited at the second step of electroplating capable of being used as a metal pad used to be wirebonded thereto or to have a gold bump or solder bump formed thereover, of being used as a metal bump, or of being used as metal vias connecting neighboring two patterned circuit layers.

2. Description of Related Arts

The continued emphasis in the semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances of semiconductor processes and materials in combination with new and sophisticated device designs. Most of the semiconductor devices are aimed at processing digital data. There are also numerous semiconductor designs that are aimed at incorporating analog functions into devices that are capable of processing digital and analog data, or devices that can be used for processing only analog data. One of the major challenges in the creation of analog processing circuitry is that a number of the components used for analog circuitry are large in size and are therefore not readily integrated into sub-micron devices. Especially, these components may be passive devices, whose size is much huge in comparison with the size of normal semiconductor devices.

Some reference teaches a process with a seed layer for two steps of electroplating, as follows;

Nobuhisa et al. (U.S. Pat. No. 6,707,159) teach a process with a seed layer for two steps of electroplating two gold layers for chip-on-chip package or for chip-on-PCB package.

Chiu-Ming et al. (US2006/0019490) teach a process with a seed layer for two steps of electroplating two gold layers, of electroplating a copper layer and a gold layer, or of electroplating a copper/gold layer and a solder layer.

Mou-Shiung Lin et al. (US2005/0277283) teach a process with a seed layer for two steps of electroplating.

SUMMARY OF THE PRESENT INVENTION

The invention provides a method for fabricating a circuitry component comprising depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; after said removing said second pattern-defining layer, removing said first metal layer not under said second metal layer; and after said removing said first metal layer, forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

The invention provides another method for fabricating a circuitry component comprising depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; and removing said second pattern-defining layer, wherein said third metal layer is used to be wirebonded thereto.

The invention provides another method for fabricating a circuitry component comprising depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a polymer layer over said second metal layer and part of said first metal layer; and removing said first metal layer not under said second metal layer and not under said polymer layer.

One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention. As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-17 are cross-sectional views showing a process with a seed layer for two steps of electroplating, wherein the metal layer deposited at the second step of electroplating is capable of being used as a metal pad used to be wirebonded thereto or to have a gold bump or solder bump formed thereover, or of being used as a metal bump.

FIGS. 18-30 are cross-sectional views showing a process with a seed layer for two steps of electroplating, wherein the metal layer deposited at the second step of electroplating is capable of being a metal via connecting neighboring two coils.

FIGS. 31-56 are cross-sectional views showing a process with a seed layer for two steps of electroplating, wherein the metal layer deposited at the second step of electroplating is capable of being a metal via connecting neighboring two circuit layers.

FIGS. 57-68 are cross-sectional views showing a process with a patterned polymer layer formed before a seed layer and adhesion/barrier layer is removed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The following are the embodiments to illustrate the processes and structures to combine the PI capping and the double embossed structure. At first, the illustrated processes and structures are applied when the PI cap is formed after the double embossed structure is finished for a semiconductor wafer.

Referring to FIG. 1, a semiconductor substrate 30 is provided, and the semiconductor substrate 30 may be Si substrate, GaAs substrate, GeSi substrate or SOI (silicon-on-insulator) substrate. The semiconductor substrate 30 is a circular semiconductor wafer. The semiconductor substrate 30 has an active surface having multiple electronic elements 32, which are formed via doping trivalent or pentavalent ions, such as boron ions or phosphorus ions. The electronic elements 32 may be MOS transistors, MOS devices, p-channel MOS devices, n-channel MOS devices, BiCMOS devices, Bipolar Junction Transistors, diffusion areas, resistors, capacitors, or CMOS devices.

Referring to FIG. 1, a multiple thin-film insulating layers 36 and multiple thin-film circuit layers 38 are formed over the active surface of the semiconductor substrate 30. Each of the thin-film insulating layers 36 has a thickness less than 3 μm. Each of the thin-film circuit layers 38 has a thickness less than 3 μm. The thin-film circuit layers 38 are made of a copper material or an aluminum material. The thin-film insulating layers 36 are usually formed with a CVD (Chemical Vapor Deposition) method. The material of the thin-film insulating layers 36 may be silicon oxide, TEOS (Tetraethoxysilane), SiwCxOyHz, compound of silicon and nitrogen/compound of silicon, nitrogen and oxygen, SOG (Spin-On Glass), FSG (Fluoro-Silicate Glass), SiLK, black diamond, polyarylene ether, PBO (Polybenzoxazole), or porous silicon oxide. The dielectric constant of the thin-film insulating layers 36 may be lower than 3.

When a damascene process is used to form one of multiple thin-film circuit layers 38, such as the topmost one under the passivation layer 42, over the semiconductor substrate 30, a diffusion-barrier layer is firstly sputtered on the upper surface of one of the thin-film insulating layers 36 and on the bottoms and the sidewalls of the openings in said one of the thin-film insulating layers 36; next, a seed layer, such as copper, is sputtered on the diffusion-barrier layer; next, another copper layer is electroplated on the seed layer; and then, the electroplated copper layer, seed layer and diffusion-barrier layer outside the openings in said one of the thin-film insulating layers 36 are removed with a chemical mechanical polishing (CMP) method until the upper surface of said one of the thin-film insulating layers 36 is exposed. In another method to form one of multiple thin-film circuit layers 38, such as the second topmost one under the passivation layer 42, over the semiconductor substrate 30, an aluminum layer or an aluminum-copper alloy layer is sputtered on one of the thin-film insulating layers 36; and then, the aluminum layer or the aluminum-copper alloy layer is patterned with photolithographic and etching processes. The thin-film circuit layers 38 can be interconnected or connected to the electronic elements 32 via conductive vias in openings in the thin-film insulating layers 36. The thickness of one of the thin-film circuit layers 38 is generally between 0.1 and 0.5 μm. The thin-film circuit layers 38 are fabricated with a 5× stepper or 5× scanner or other superior equipment in the step of a photolithographic process.

Next, a passivation layer 42 is formed over the thin-film insulating layers 36 and the thin-film circuit layers 38 with a CVD method. The passivation layer 42 can protect the electronic elements 32 in the semiconductor substrate 30 from foreign ion contamination. The passivation layer 42 can retard the penetration of mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, and copper) and impurities. Thereby, the passivation layer 42 can protect the thin-film circuit layers 38, the thin-film insulating layers 36 and the underlying electronic elements 32 including: transistors, polysilicon resistors, polysilicon-polysilicon capacitors. The passivation layer 42 is usually composed of silicon oxide, compounds of silicon and oxygen, silicate and phosphate glass, silicon nitride, or silicon oxy-nitride, etc. Below, ten methods for depositing the passivation layer 42 are to be introduced.

Method 1

A silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed with a CVD method; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxide with a CVD method.

Method 2

A silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed with a CVD method; next, a silicon oxy-nitride layer with a thickness of between 0.05 and 0.15 μm is formed on the silicon oxide with a plasma-enhanced CVD method; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxy-nitride layer with a CVD method.

Method 3

A silicon oxy-nitride layer with a thickness of between 0.05 and 0.15 μm is formed with a CVD method; next, a silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxy-nitride layer with a CVD method; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxide layer with a CVD method.

Method 4

A first silicon oxide layer with a thickness of between 0.2 and 0.5 μm is formed with a CVD method; next, a second silicon oxide layer with a thickness of between 0.5 and 1 μm is formed on the first silicon oxide layer with a spin-coating method; next, a third silicon oxide layer with a thickness of between 0.2 and 0.5 μm is formed on the second silicon oxide layer with a CVD method; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the third silicon oxide layer with a CVD method.

Method 5

A silicon oxide layer with a thickness of between 0.5 and 2 μm is formed with a HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxide layer with a CVD method.

Method 6

A USG (Undopcd Silicate Glass) layer with a thickness of between 0.2 and 3 μm is firstly formed; next, an insulating layer with a thickness of between 0.5 and 3 μm, such as TEOS, BPSG (Borophosphosilicate Glass) or PSG (Borophosphosilicate Glass), is formed on the USG layer; and next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the insulating layer with a CVD method.

Method 7

A first silicon oxy-nitride layer with a thickness of between 0.05 and 0.15 μm is optionally formed with a CVD method; next, a silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the first silicon oxy-nitride layer with a CVD method; next, a second silicon oxy-nitride layer with a thickness of between 0.05 and 0.15 μm is optionally formed on the silicon oxide layer with a CVD method; next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the second silicon oxy-nitride layer or on the silicon oxide layer with a CVD method; next, a third silicon oxy-nitride layer with a thickness of between 0.05 and 0.15 μm is optionally formed on the silicon nitride layer with a CVD method; and next, a silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the third silicon oxy-nitride layer or on the silicon nitride layer with a CVD method.

Method 8

A first silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed with a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; next, a second silicon oxide layer with a thickness of between 0.5 and 1 μm is formed on the first silicon oxide layer with a spin-coating method; next, a third silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the second silicon oxide layer with a CVD method; next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the third silicon oxide layer with a CVD method; and next, a fourth silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon nitride layer with a CVD method.

Method 9

A first silicon oxide layer with a thickness of between 0.5 and 2 μm is formed with a HDP-CVD method; next, a silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the first silicon oxide layer with a CVD method; and next, a second silicon oxide layer with a thickness of between 0.5 and 2 μm is formed on the silicon nitride layer with a HDP-CVD method.

Method 10

A first silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed with a CVD method; next, a silicon oxide layer with a thickness of between 0.2 and 1.2 μm is formed on the first silicon nitride layer with a CVD method; and next, a second silicon nitride layer with a thickness of between 0.2 and 1.2 μm is formed on the silicon oxide layer with a CVD method.

The total thickness of the passivation layer 42 is generally more than 0.35 μm, and the thickness of the silicon nitride layer is generally more than 0.3 μm under an optimal condition. Typically, the passivation layer 42 comprises a topmost silicon-nitride layer of the completed semiconductor wafer or chip. The passivation layer 42 comprises a topmost silicon-oxide layer of the completed semiconductor wafer or chip. The passivation layer 42 comprises a topmost silicon-oxynitride layer of the completed semiconductor wafer or chip. The passivation layer 42 comprises a topmost CVD-formed layer of the completed semiconductor wafer or chip.

Referring to FIG. 2, it is an optional process to form two patterned polymer layers 220 and 230 on the passivation layer 42. The patterned first polymer layer 220 can be formed by spin coating a first polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the passivation layer 42.

Next, if the spin-coated first polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to pattern the spin-coated first polymer layer. Next, the first polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated first polymer layer is polyimide. The patterned first polymer layer 220 after being cured may have a thickness t1 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated first polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated first polymer layer.

Alternatively, the patterned first polymer layer 220 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the passivation layer 42, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned first polymer layer 220 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the passivation layer 42.

If the patterned first polymer layer 220 is not thick enough, a patterned second polymer layer 230 can be formed on the patterned first polymer layer 220, as shown in FIG. 2. The patterned second polymer layer 230 can be formed by spin coating a second polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the patterned first polymer layer 220 and on the passivation layer 42.

Next, if the spin-coated second polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to pattern the spin-coated second polymer layer. Next, the first polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated second polymer layer is polyimide. The patterned second polymer layer 230 after being cured may have a thickness t2 of between 6 and 20 microns, and preferably between 6 and 20 microns.

If the spin-coated second polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated second polymer layer.

Alternatively, the patterned second polymer layer 230 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the patterned first polymer layer 220, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned second polymer layer 230 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 10 and 500 microns on the patterned first polymer layer 220.

Referring to FIG. 2, after forming the patterned first and second polymer layers 220 and 230, an adhesion/barrier layer 340 may be formed by sputtering or evaporating a metal layer of titanium, tungsten, cobalt, nickel, titanium nitride, a titanium-tungsten alloy, chromium, a chromium-copper alloy, tantalum, or tantalum nitride, with a thickness of between 1000 and 6000 angstroms, on the patterned second polymer layer 230 and on the passivation layer 42. Next, a seed layer 342 may be formed by sputtering, evaporating or electroless plating a metal layer of gold, copper, nickel, silver, palladium, platinum, rhodium, ruthenium, or rhenium, with a thickness of between 500 and 3000 angstroms on the adhesion/barrier layer 340.

Next, referring to FIG. 3, a photoresist layer 350, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t3 of between 4 and 30 microns, is formed on the seed layer 342 using a spin coating process.

Next, referring to FIG. 4, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 350 and to form an opening 352, with a coil pattern from a top view, in the photoresist layer 350 exposing the seed layer 342.

Next, referring to FIG. 5, a metal layer 360, with a coil pattern from a top view, is electroplated on seed layer 342 exposed by the opening 352 in the photoresist layer 350. The metal layer 360 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns, and preferably between 3 and 10 microns, on the seed layer 342 preferably of gold exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of copper exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of silver exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of nickel with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of nickel exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of palladium exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of platinum exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of rhodium exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of ruthenium exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a single layer of rhenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of rhenium exposed by the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of copper exposed by the opening 352 in the photoresist layer 350, and then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the opening 352 in the photoresist layer 350. Alternatively, the metal layer 360 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 342 preferably of copper exposed by the opening 352 in the photoresist layer 350, then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the opening 352 in the photoresist layer 350, and then electroplating a gold layer with a thickness of between 1 and 5 microns on the nickel layer in the opening 352 in the photoresist layer 350.

Next, referring to FIG. 6, the photoresist layer 350 is stripped. The pitch p1 between the centers of the neighboring turns of the patterned coil may range from 2 to 30 microns, and preferably from 2 and 10 microns.

Next, referring to FIG. 7, a photoresist layer 370, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t4 of between 4 and 30 microns, is formed on the electroplated metal layer 360 and on the seed layer 342 using a spin coating process.

Next, referring to FIG. 8, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 370 and to form an opening 372 in the photoresist layer 370 exposing the electroplated metal layer 360.

Next, referring to FIG. 9, a metal layer 380 is electroplated on the metal layer 360 exposed by the opening 372 in the photoresist layer 370. The metal layer 380 can be deposited by electroplating a single layer of gold with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably gold, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 30 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of silver with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably silver, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of palladium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably palladium, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of platinum with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably platinum, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of rhodium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably rhodium, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of ruthenium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably ruthenium, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of rhenium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably rhenium, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a single layer of copper with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably copper, exposed by the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 372 in the photoresist layer 370, and then electroplating a solder layer, such a tin-lead alloy or a tin-silver alloy, with a thickness of between 10 and 150 microns on the nickel layer in the opening 372 in the photoresist layer 370. Alternatively, the metal layer 380 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 372 in the photoresist layer 370, and then electroplating a gold layer with a thickness of between 1 and 20 microns on the nickel layer in the opening 372 in the photoresist layer 370.

Next, referring to FIG. 10, the photoresist layer 370 is stripped. Next, referring to FIG. 11, the seed layer 342 not under the metal layer 360 is removed using a dry etching process or a wet etching process. If the seed layer 342 is gold and removed by a wet etching process, the etchant for etching the seed layer 342 is potassium iodide. Thereafter, the adhesion/barrier layer 340 not under the metal layer 360 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 340 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 340 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrofluoric acid.

Referring to FIGS. 12-13, it is an optional process to form a patterned polymer layer 390 on the metal layers 380 and 360, on the patterned polymer layer 330, and on the passivation layer 42. The patterned polymer layer 390 can be formed by spin coating a polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layers 380 and 360, on the patterned polymer layer 330, and on the passivation layer 42.

Next, if the spin-coated polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to form an opening 392 in the spin-coated polymer layer exposing the metal layer 380. Next, the spin-coated polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. The patterned polymer layer 390 after being cured may have a thickness t5 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated polymer layer.

Alternatively, the patterned polymer layer 390 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layer 360, on the patterned polymer layer 330, and on the passivation layer 42, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned polymer layer 390 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layer 360, on the patterned polymer layer 330, and on the passivation layer 42.

In this embodiment, the patterned polymer layer 390 covers the peripheral region of the metal layer 380 used as a metal pad.

Next, referring to FIG. 14, the metal layer 380 is used as a metal pad for being wirebonded thereto or having a gold bump or solder bump formed thereover. A gold wire 394 can be connected to the metal layer 380 exposed by the opening 392 in the polymer layer 390 using a wirebonding process. Alternatively, a gold bump or tin-containing bump, not shown, can be formed over the above-mentioned metal layer 380 exposed by the opening 392 in the polymer layer 390.

Alternatively, referring to FIG. 15, the metal layer 380 used as a metal pad for being wirebonded thereto or having a gold bump or solder bump formed thereover has a top surface and a side surface not covered by the patterned polymer layer 390. A gold wire 394 can be connected to the metal layer 380 exposed by the opening 392 in the polymer layer 390 using a wirebonding process. Alternatively, a gold bump or tin-containing bump, not shown, can be formed over the above-mentioned metal layer 380 exposed by the opening 392 in the polymer layer 390. The elements shown in FIG. 15 having same reference numbers as those shown in FIGS. 1-14 indicate similar ones described above in FIGS. 1-14.

Alternatively, referring to FIG. 16, the above-mentioned metal layer 380 may be used as a metal bump capable of being connected to an external circuitry 396, such as a ceramic substrate, a printed circuit board, semiconductor chip for chip-on-chip package, glass substrate for a chip-on-glass (COG) package, flex circuit substrate for a chip-on-film (COF) package, a tape carrier for tape-automated-bonded (TAB) package. In the application for COG, COF or TAB packages, the topmost layer of the metal layer 380 is preferably gold, which can be bonded to a metal layer 398, preferably of gold, formed on the above-mentioned external circuitry 396 or to a metal layer 398, preferably of tin-containing material, formed on the above-mentioned external circuitry. Alternatively, an anisotropic conductive film (ACF) can be use to electrically connect the metal layer 380 to the above-mentioned external circuitry 396, such as glass substrate. In the application for being connected to a ceramic substrate, printed circuit board, or semiconductor chip 396, the topmost layer of the metal layer 380 is preferably tin-containing material, which can be bonded to a metal layer 398, preferably of gold, formed on the ceramic substrate, printed circuit board, or semiconductor chip 396, or to a metal layer 398, preferably of tin-containing material, formed on the ceramic substrate, printed circuit board, or semiconductor chip 396. After the metal layer 380 is connected to the above-mentioned external circuitry 396, a polymer material 399, such as polyimide or benzo-cyclo-butene (BCB), can be filled into the gap between the patterned polymer layer 390 and the above-mentioned external circuitry 396. The metal layer 380 used as a metal bump is protruded from the patterned polymer layer 390 such that the metal layer 380 can be easily bonded to the above-mentioned external circuitry 396. The elements shown in FIG. 16 having same reference numbers as those shown in FIGS. 1-14 indicate similar ones described above in FIGS. 1-14.

Alternatively, referring to FIG. 17, a metal bump formed from the above-mentioned metal layer 380 capable of being connected to the above-mentioned external circuitry 396 and a bond pad formed from the above-mentioned metal layer 360 capable of being wirebonded thereto or having a gold bump or solder bump formed thereover can be provided. An opening 393 in the polymer layer 390 exposes the bond pad formed from the above-mentioned metal layer 360. A gold wire 394 can be connected to the metal layer 360 exposed by the opening 393 in the polymer layer 390 using a wirebonding process. Alternatively, a gold bump or tin-containing bump, not shown, can be formed over the metal layer 360 exposed by the opening 393 in the polymer layer 390. The elements shown in FIG. 17 having same reference numbers as those shown in FIGS. 1-14 and 16 indicate similar ones described above in FIGS. 1-14 and 16.

Alternatively, two layers of coils can be formed over the passivation layer 42, as shown in FIGS. 18-30. The process illustrated by FIGS. 18-30 follows the above-mentioned process of FIG. 6. The elements shown in FIGS. 18-30 having same reference numbers as those shown in FIGS. 1-14 indicate similar ones described above in FIGS. 1-14. After the above-mentioned metal layer 360 is formed, a photoresist layer 470, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t4 of between 1 and 30 microns, is formed on the electroplated metal layer 360 and on the seed layer 342 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 470 and to form an opening 472 in the photoresist layer 470 exposing the electroplated metal layer 360.

Next, a metal layer 480 is electroplated on the metal layer 360 exposed by the opening 472 in the photoresist layer 470. The metal layer 480 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably gold, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably silver, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably palladium, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably platinum, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably rhodium, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably ruthenium, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of rhenium with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably rhenium, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns on the metal layer 360, whose topmost layer is preferably copper, exposed by the opening 472 in the photoresist layer 470. Alternatively, the metal layer 480 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 472 in the photoresist layer 470, and then electroplating a solder layer, such a tin-lead alloy or a tin-silver alloy, with a thickness of between 1 and 10 microns on the nickel layer. Alternatively, the metal layer 480 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 472 in the photoresist layer 470, and then electroplating a gold layer with a thickness of between 1 and 10 microns on the nickel layer.

In the embodiment, the metal layer 480 is formed with a metal via connecting neighboring coils separated by a to-be-formed polymer layer.

Next, referring to FIG. 19, the photoresist layer 470 is stripped. Next, referring to FIG. 20, the seed layer 342 not under the metal layer 360 is removed using a dry etching process or a wet etching process. If the seed layer is gold and removed by a wet etching process, the etchant for etching the seed layer 342 is potassium iodide. Thereinafter, the adhesion/barrier layer 340 not under the metal layer 360 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 340 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 340 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrofluoric acid.

Referring to FIG. 21, a polymer layer 490 is formed on the metal layers 480 and 360, on the patterned polymer layer 330, and on the passivation layer 42. The polymer layer 490 can be formed by spin coating a polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layers 380 and 360, on the patterned polymer layer 330, and on the passivation layer 42, and then curing the spin-coated polymer layer at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. Alternatively, the polymer layer 490 can be formed by repeating said spin coating process and said curing process many times to form the polymer layer 490 with an extremely great thickness.

Alternatively, the polymer layer 490 can be formed by screen printing a polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layers 480 and 360, on the patterned polymer layer 330, and on the passivation layer 42, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the polymer layer 490 can be formed by laminating a dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layers 480 and 360, on the patterned polymer layer 330, and on the passivation layer 42.

Next, referring to FIG. 22, the top side of the polymer layer 490 is ground using a mechanical grinding process or using a chemical mechanical polishing (CMP) process until the top surface of the metal layer 480 is exposed to the outside.

Next, referring to FIG. 23, an adhesion/barrier layer 540 may be formed by sputtering or evaporating a metal layer of titanium, tungsten, cobalt, nickel, titanium nitride, a titanium-tungsten alloy, chromium, a chromium-copper alloy, tantalum, or tantalum nitride, with a thickness of between 1000 and 6000 angstroms, on the polymer layer 490 and on the metal layer 480. Next, a seed layer 542 may be formed by sputtering, evaporating or electroless plating a metal layer of gold, copper, nickel, silver, palladium, platinum, rhodium, ruthenium, or rhenium, with a thickness of between 500 and 3000 angstroms on the adhesion/barrier layer 540.

Next, referring to FIG. 24, a photoresist layer 550, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t3 of between 4 and 30 microns, is formed on the seed layer 542 using a spin coating process.

Next, referring to FIG. 25, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 550 and to form an opening 552, with a coil pattern from a top view, in the photoresist layer 550 exposing the seed layer 542.

Next, referring to FIG. 26, a metal layer 560, with a coil pattern from a top view, is electroplated on seed layer 542 exposed by the opening 552 in the photoresist layer 550. The metal layer 560 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns, and preferably between 3 and 10 microns, on the seed layer 542 preferably of gold exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of copper exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of silver exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of nickel with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of nickel exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of palladium exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of platinum exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of rhodium exposed by the opening 552 in the photoresist layer 550: Alternatively, the metal layer 560 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of ruthenium exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a single layer of rhenium with a thickness of between and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of rhenium exposed by the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of copper exposed by the opening 552 in the photoresist layer 550, and then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the opening 552 in the photoresist layer 550. Alternatively, the metal layer 560 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 542 preferably of copper exposed by the opening 552 in the photoresist layer 550, then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the opening 552 in the photoresist layer 550, and then electroplating a gold layer with a thickness of between 1 and 5 microns on the nickel layer in the opening 552 in the photoresist layer 550.

Next, referring to FIG. 27, the photoresist layer 550 is stripped. The pitch p2 between the centers of the neighboring turns of the patterned coil may range from 2 to 30 microns, and preferably from 2 and 10 microns.

Next, referring to FIG. 28, the seed layer 542 not under the metal layer 560 is removed using a dry etching process or a wet etching process. If the seed layer 542 is gold and removed by a wet etching process, the etchant for etching the seed layer 542 is potassium iodide. Thereafter, the adhesion/barrier layer 540 not under the metal layer 560 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 540 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 540 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 540 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 540 is hydrofluoric acid.

Referring to FIGS. 29-30, it is an optional process to form a patterned polymer layer 590 on the metal layer 560 and on the polymer layer 490. The patterned polymer layer 590 can be formed by spin coating a polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layer 560 and on the polymer layer 490.

Next, if the spin-coated polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to form an opening 592 in the spin-coated polymer layer exposing the metal layer 560. Next, the spin-coated polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. The patterned polymer layer 590 after being cured may have a thickness t6 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated polymer layer.

Alternatively, the patterned polymer layer 590 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layer 560 and on the polymer layer 490, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned polymer layer 590 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layer 560 and on the polymer layer 490.

Next, referring to FIG. 30, the metal layer 560 has a portion exposed by the opening 592 in the polymer layer 590, which may be used as a metal pad for being wirebonded thereto or having a gold bump or solder bump formed thereover. A gold wire 394 can be connected to the metal layer 560 exposed by the opening 592 in the polymer layer 590 using a wirebonding process. Alternatively, a gold bump or tin-containing bump, not shown, can be formed over the above-mentioned metal layer 560 exposed by the opening 592 in the polymer layer 590.

Alternatively, the above-mentioned process is not limited to forming coils with two patented circuit layers, but can be applied to forming a metal trace with multiple patterned circuit layers, as shown in FIG. 31-56. Referring to FIGS. 31-56, the structure under the passivation layer 42 can be referred as to that described in FIG. 1. The elements shown in FIGS. 31-56 having same reference numbers as those shown in FIGS. 1-14 indicate similar ones described above in FIGS. 1-14. In FIG. 31, multiple openings 44 may be formed in the passivation layer 42 and may expose multiple metal pads of the topmost one of the thin-film circuit layers 38.

Referring to FIG. 32, it is an optional process to form a patterned polymer layer 620 on the passivation layer 42 and on the metal pads exposed by the openings 44 in the passivation layer 42. The patterned polymer layer 620 can be formed by spin coating a polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the passivation layer 42 and on the metal pads of the topmost one of the thin-film circuit layers 38 exposed by the openings 44 in the passivation layer 42.

Next, if the spin-coated polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to pattern the spin-coated polymer layer and to form multiple openings 622 in the spin-coated polymer layer exposing the metal pads of the topmost one of the thin-film circuit layers 38 exposed by the openings 44 in the passivation layer 42. Next, the spin-coated polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. The patterned polymer layer 620 after being cured may have a thickness t7 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated first polymer layer.

Alternatively, the patterned polymer layer 620 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the passivation layer 42, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned polymer layer 620 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the passivation layer 42.

The patterned polymer layer 620 may cover a peripheral region of the exposed surface of the metal pads, such as the left one, of the topmost one of the thin-film circuit layers 38 exposed by the openings 44 in the passivation layer 42. The openings 622 in the patterned polymer layer 620 may expose the entire exposed surface of the metal pads, such as the middle and right ones, of the topmost one of the thin-film circuit layers 38 exposed by the openings 44 in the passivation layer 42.

Alternatively, the patterned polymer layer 620 can be formed by repeating said spin coating process and said curing process many times to form the polymer layer 620 with an extremely great thickness.

Referring to FIG. 33, after forming the patterned polymer layer 620, an adhesion/barrier layer 640 may be formed by sputtering or evaporating a metal layer of titanium, tungsten, cobalt, nickel, titanium nitride, a titanium-tungsten alloy, chromium, a chromium-copper alloy, tantalum, or tantalum nitride, with a thickness of between 1000 and 6000 angstroms, on the patterned polymer layer 620 and on the metal pads of the topmost one of the thin-film circuit layers 38 exposed by the openings 44 in the passivation layer 42. Next, a seed layer 642 may be formed by sputtering, evaporating or electroless plating a metal layer of gold, copper, nickel, silver, palladium, platinum, rhodium, ruthenium, or rhenium, with a thickness of between 500 and 3000 angstroms on the adhesion/barrier layer 640.

Next, referring to FIG. 34, a photoresist layer 650, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t8 of between 4 and 30 microns, is formed on the seed layer 642 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 650 and to form multiple openings 652, with trace patterns from a top view, in the photoresist layer 650 exposing the seed layer 642.

Next, referring to FIG. 35, a metal layer 660, with a coil pattern from a top view, is electroplated on seed layer 642 exposed by the openings 652 in the photoresist layer 650. The metal layer 660 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns, and preferably between 3 and 10 microns, on the seed layer 642 preferably of gold exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of copper exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of silver exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of nickel with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of nickel exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of palladium exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of platinum exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of rhodium exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of ruthenium exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a single layer of rhenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 642 preferably of rhenium exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer preferably of copper exposed by the openings 652 in the photoresist layer 650, and then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer exposed by the openings 652 in the photoresist layer 650. Alternatively, the metal layer 660 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer preferably of copper exposed by the openings 652 in the photoresist layer 650, then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer exposed by the openings in the photoresist layer 650, and then electroplating a gold layer with a thickness of between 1 and 5 microns on the nickel layer exposed by the openings in the photoresist layer 650.

Next, referring to FIG. 36, the photoresist layer 650 is stripped.

Next, referring to FIG. 37, a photoresist layer 670, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t9 of between 4 and 30 microns, is formed on the electroplated metal layer 660 and on the seed layer 642 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 670 and to form multiple openings 672 in the photoresist layer 670 exposing the electroplated metal layer 660.

Next, referring to FIG. 38, a metal layer 680 is electroplated on the metal layer 660 exposed by the openings 672 in the photoresist layer 670. The metal layer 680 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably gold, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably nickel, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably silver, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably palladium, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably platinum, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably rhodium, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably ruthenium, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of rhenium with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably rhenium, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns on the metal layer 660, whose topmost layer is preferably copper, exposed by the openings 672 in the photoresist layer 670. Alternatively, the metal layer 680 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 660, whose topmost layer is preferably nickel, exposed by the openings 672 in the photoresist layer 670, and then electroplating a solder layer, such a tin-lead alloy or a tin-silver alloy, with a thickness of between 1 and 10 microns on the nickel layer. Alternatively, the metal layer 680 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 660, whose topmost layer is preferably nickel, exposed by the openings 672 in the photoresist layer 670, and then electroplating a gold layer with a thickness of between 1 and 10 microns on the nickel layer.

In the embodiment, the metal layer 680 is formed with multiple metal vias connecting neighboring circuit metal layers separated by a to-be-formed polymer layer.

Next, referring to FIG. 39, the photoresist layer 670 is stripped. Next, referring to FIG. 40, the seed layer 642 not under the metal layer 660 is removed using a dry etching process or a wet etching process. If the seed layer 642 is gold and removed by a wet etching process, the etchant for etching the seed layer 642 is potassium iodide. Thereafter, the adhesion/barrier layer 340 not under the metal layer 660 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 640 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 640 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 640 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 640 is hydrofluoric acid.

Referring to FIG. 41, a polymer layer 690 is formed on the metal layers 680 and 660 and on the patterned polymer layer 620. The polymer layer 690 can be formed by spin coating a polymer layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layers 680 and 660 and on the patterned polymer layer 620, and then curing the spin-coated polymer layer at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. Alternatively, the polymer layer 690 can be formed by repeating said spin coating process and said curing process many times to form the polymer layer 690 with an extremely great thickness.

Alternatively, the polymer layer 690 can be formed by screen printing a polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layers 680 and 660 and on the patterned polymer layer 620, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the polymer layer 690 can be formed by laminating a dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layers 680 and 660 and on the patterned polymer layer 620.

Next, referring to FIG. 42, the top side of the polymer layer 690 is ground using a mechanical grinding process or using a chemical mechanical polishing (CMP) process until the top surface of the metal layer 680 is exposed to the outside.

Next, referring to FIG. 43, an adhesion/barrier layer 740 may be formed by sputtering or evaporating a metal layer of titanium, tungsten, cobalt, nickel, titanium nitride, a titanium-tungsten alloy, chromium, a chromium-copper alloy, tantalum, or tantalum nitride, with a thickness of between 1000 and 6000 angstroms, on the polymer layer 690 and on the metal layer 680. Next, a seed layer 742 may be formed by sputtering, evaporating or electroless plating a metal layer of gold, copper, nickel, silver, palladium, platinum, rhodium, ruthenium, or rhenium, with a thickness of between 500 and 3000 angstroms on the adhesion/barrier layer 740.

Next, referring to FIG. 44, a photoresist layer 750, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t9 of between 4 and 30 microns, is formed on the seed layer 742 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 750 and to form an opening 752, with trace patterns from a top view, in the photoresist layer 750 exposing the seed layer 742.

Next, referring to FIG. 45, a metal layer 760, with trace patterns from a top view, is electroplated on seed layer 742 exposed by the openings 752 in the photoresist layer 750. The metal layer 760 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 20 microns, and preferably between 3 and 10 microns, on the seed layer 742 preferably of gold exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of copper with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of copper exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of silver with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of silver exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of nickel with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of nickel exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of palladium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of palladium exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of platinum with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of platinum exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of rhodium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of rhodium exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of ruthenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of ruthenium exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a single layer of rhenium with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of rhenium exposed by the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of copper exposed by the openings 752 in the photoresist layer 750, and then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the openings 752 in the photoresist layer 750. Alternatively, the metal layer 760 can be deposited by electroplating a copper layer with a thickness of between 1 and 20 microns, and preferably 3 and 10 microns, on the seed layer 742 preferably of copper exposed by the openings 752 in the photoresist layer 750, then electroplating a nickel layer with a thickness of between 1 and 5 microns on the copper layer in the openings 752 in the photoresist layer 750, and then electroplating a gold layer with a thickness of between 1 and 5 microns on the nickel layer in the openings 752 in the photoresist layer 750.

Next, referring to FIG. 46, the photoresist layer 750 is stripped.

Next, referring to FIG. 47, a photoresist layer 770, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t10 of between 4 and 30 microns, is formed on the electroplated metal layer 760 and on the seed layer 742 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 770 and to form an opening 772 in the photoresist layer 770 exposing the electroplated metal layer 760.

Next, referring to FIG. 48, a metal layer 780 formed for a metal pad used to be wirebonded thereto is electroplated on the metal layer 760 exposed by the opening 772 in the photoresist layer 770. The metal layer 780 can be deposited by electroplating a single layer of gold with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably gold, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 30 microns on the metal layer 760, whose topmost layer is preferably nickel, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of silver with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably silver, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of palladium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably palladium, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of platinum with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably platinum, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of rhodium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably rhodium, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of ruthenium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably ruthenium, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of rhenium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably rhenium, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a single layer of copper with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably copper, exposed by the opening 772 in the photoresist layer 770. Alternatively, the metal layer 780 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 760, whose topmost layer is preferably nickel, exposed by the opening 772 in the photoresist layer 770, and then electroplating a gold layer with a thickness of between 1 and 20 microns on the nickel layer.

Next, referring to FIG. 49, the photoresist layer 770 is stripped.

Next, referring to FIG. 50, a photoresist layer 790, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t11 of between 4 and 30 microns, is formed on the electroplated metal layers 760 and 780 and on the seed layer 742 using a spin coating process. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 790 and to form an opening 792 in the photoresist layer 790 exposing the electroplated metal layer 760.

Next, referring to FIG. 51, a metal layer 794 formed for a metal bump is electroplated on the metal layer 760 exposed by the opening 792 in the photoresist layer 790. The metal layer 794 can be deposited by electroplating a single layer of gold with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably gold, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 30 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of silver with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably silver, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of palladium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably palladium, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of platinum with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably platinum, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of rhodium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably rhodium, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of ruthenium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably ruthenium, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of rhenium with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably rhenium, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a single layer of copper with a thickness of between 2 and 30 microns on the metal layer 760, whose topmost layer is preferably copper, exposed by the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 760, whose topmost layer is preferably nickel, exposed by the opening 792 in the photoresist layer 790, and then electroplating a solder layer, such a tin-lead alloy or a tin-silver alloy, with a thickness of between 10 and 150 microns on the nickel layer in the opening 792 in the photoresist layer 790. Alternatively, the metal layer 794 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 760, whose topmost layer is preferably nickel, exposed by the opening 792 in the photoresist layer 790, and then electroplating a gold layer with a thickness of between 1 and 20 microns on the nickel layer in the opening 792 in the photoresist layer 790.

Next, referring to FIG. 52, the photoresist layer 790 is stripped. Next, referring to FIG. 53, the seed layer 742 not under the metal layer 760 is removed using a dry etching process or a wet etching process. If the seed layer 742 is gold and removed by a wet etching process, the etchant for etching the seed layer 742 is potassium iodide. Thereafter, the adhesion/barrier layer 740 not under the metal layer 760 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 740 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 740 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 740 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 740 is hydrofluoric acid.

Referring to FIGS. 54-55, it is an optional process to form a patterned polymer layer 796 on the metal layers 794, 780 and 760 and on the patterned polymer layer 690. The patterned polymer layer 796 can be formed by spin coating a polyiner layer of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layers 794, 780 and 760 and on the patterned polymer layer 690.

Next, if the spin-coated polymer layer is photosensitive, a photolithography process including exposing and developing steps can be used to lead the metal layers 794 and 780 to be exposed to the outside. Next, the spin-coated polymer layer is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer is polyimide. The patterned polymer layer 796 after being cured may have a thickness t12 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated polymer layer is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated polymer layer.

Alternatively, the patterned polymer layer 796 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layer 760 and on the patterned polymer layer 690, and then curing the screen-printed polymer layer at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer is polyimide. Alternatively, the patterned polymer layer 796 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layer 760 and on the patterned polymer layer 690.

Next, referring to FIG. 56, the metal layer 780 is used as a metal pad for being wirebonded thereto. A gold wire 394 can be connected to the metal layer 780. The metal layer 794 is formed for a metal bump used to be bonded to an external circuitry (not shown), such as a ceramic substrate, a printed circuit board, semiconductor chip for chip-on-chip package, glass substrate for a chip-on-glass (COG) package, flex circuit substrate for a chip-on-film (COF) package, a tape carrier for tape-automated-bonded (TAB) package. In the application for COG, COF or TAB packages, the topmost layer of the metal layer 794 is preferably gold, which can be bonded to a metal layer, preferably of gold, formed on the above-mentioned external circuitry or to a metal layer, preferably of tin-containing material, formed on the above-mentioned external circuitry. Alternatively, an anisotropic conductive film (ACF) can be use to electrically connect the metal layer 794 to the above-mentioned external circuitry, such as glass substrate. In the application for being connected to a ceramic substrate, printed circuit board, or semiconductor chip, the topmost layer of the metal layer 794 is preferably tin-containing material, which can be bonded to a metal layer, preferably of gold, formed on the ceramic substrate, printed circuit board, or semiconductor chip, or to a metal layer, preferably of tin-containing material, formed on the ceramic substrate, printed circuit board, or semiconductor chip.

Alternatively, a polymer layer covering a metal trace, such as a coil, can be formed before removing the seed layer and the adhesion/barrier layer not under the metal trace, as shown in FIGS. 57-60. The process illustrated by FIGS. 57-60 follows the above-mentioned process of FIG. 6. The elements shown in FIGS. 57-60 having same reference numbers as those shown in FIGS. 1-14 indicate similar ones described above in FIGS. 1-14. After the above-mentioned metal layer 360 is formed, a patterned polymer layer 830 is formed on the metal layer 360 and on the seed layer 342. The patterned polymer layer 830 can be formed by spin coating a polymer layer 832 of polyimide, benzo-cyclo-butene (BCB), parylene-based material, epoxy-based material, or elastomer, with a thickness of between 2 and 50 microns, and preferably between 8 and 30 microns, on the metal layer 360 and on the seed layer 342, as shown in FIG. 57.

Next, if the spin-coated polymer layer 832 is photosensitive, a photolithography process including exposing and developing steps can be used to lead the spin-coated polymer layer 830 on the metal layer 360 and on the seed layer close to the metal layer 360 to be left and to form an opening 834 in the spin-coated polymer layer 830 exposing the metal layer 360, as shown in FIG. 58. Next, the spin-coated polymer layer 830 is cured at the temperature of 300 and 450 degrees centigrade if the spin-coated polymer layer 830 is polyimide. The patterned polymer layer 830 after being cured may have a thickness t13 of between 2 and 50 microns, and preferably between 6 and 20 microns.

If the spin-coated polymer layer 832 is non-photosensitive, photolithography and etching processes are typically needed to pattern the spin-coated polymer layer 832.

Alternatively, the patterned polymer layer 830 can be formed by screen printing a patterned polymer layer of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy-based material, with a thickness of between 5 and 50 microns on the metal layer 360 and on the seed layer 342 close to the metal layer 360, and then curing the screen-printed polymer layer 830 at the temperature of 300 and 450 degrees centigrade if the screen-printed polymer layer 830 is polyimide. Alternatively, the patterned polymer layer 830 can be formed by laminating a patterned dry film of polyimide, benzocyclobutene (BCB), parylene-based material or epoxy, with a thickness of between 10 and 500 microns on the metal layer 360 and on the seed layer 342 close to the metal layer 360.

Next, referring to FIG. 59, the seed layer 342 not under the metal layer 360 and not under the patterned polymer layer 830 is removed using a dry etching process or a wet etching process. If the seed layer 342 is gold and removed by a wet etching process, the etchant for etching the seed layer 342 is potassium iodide. Thereafter, the adhesion/barrier layer 340 not under the metal layer 360 and not under the patterned polymer layer 830 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 340 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrogen peroxide or hydrofluoric acid. If the adhesion/barrier layer 340 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrofluoric acid.

Next, referring to FIG. 60, the metal layer 360 has a metal pad exposed by the opening 834 in the patterned polymer layer 830, for being wirebonded thereto or having a gold bump or solder bump formed thereover. A gold wire 394 can be connected to the metal layer 360 exposed by the opening 834 in the polymer layer 830 using a wirebonding process. Alternatively, a gold bump or tin-containing bump, not shown, can be formed over the above-mentioned metal layer 360 exposed by the opening 834 in the polymer layer 830.

Alternatively, a metal layer, for a metal bump used to be bonded to an external circuitry or a metal pad used to be wirebonded thereto, can be electroplated over the metal layer 360 after forming the patterned polymer layer 830 and before removing the seed layer 342 and adhesion/barrier layer 340 not under the metal layer 360 and not under the patterned polymer layer 830, as shown in FIGS. 61-65. The process illustrated by FIGS. 61-65 follows the above-mentioned process of FIG. 58. The elements shown in FIGS. 61-65 having same reference numbers as those shown in FIGS. 1-14 and 57-58 indicate similar ones described above in FIGS. 1-14 and 57-58. After the patterned polymer layer 830 is formed on the metal layer 360 and on the seed layer 342 close to the metal layer 360, a photoresist layer 870, such as photosensitive polyimide, photosensitive benzo-cyclo-butene (BCB), photosensitive parylene-based material, photosensitive epoxy-based material, with a thickness t14 of between 4 and 30 microns, is formed on the seed layer 342, on the patterned polymer layer 830 and on the metal layer 360 exposed by the opening 834 in the patterned polymer layer 830 using a spin coating process, referring to FIG. 61. Next, a photolithography process including exposing and developing steps is used to pattern the photoresist layer 870 and to form an opening 872 in the photoresist layer 870 exposing the electroplated metal layer 360 exposed by the opening 834 in the patterned polymer layer 830.

Next, referring to FIG. 62, a metal layer 880 is electroplated on the metal layer 360 exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. The metal layer 880 can be deposited by electroplating a single layer of gold with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably gold, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of gold with a thickness of between 1 and 30 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of silver with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably silver, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of palladium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably palladium, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of platinum with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably platinum, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of rhodium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably rhodium, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of ruthenium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably ruthenium, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of rhenium with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably rhenium, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a single layer of copper with a thickness of between 2 and 30 microns on the metal layer 360, whose topmost layer is preferably copper, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 872 in the photoresist layer 870 and by the opening 834 in the patterned polymer layer 830, and then electroplating a solder layer, such a tin-lead alloy or a tin-silver alloy, with a thickness of between 10 and 150 microns on the nickel layer in the opening 872 in the photoresist layer 870 and/or in the opening 834 in the patterned polymer layer 830. Alternatively, the metal layer 880 can be deposited by electroplating a nickel layer with a thickness of between 1 and 10 microns on the metal layer 360, whose topmost layer is preferably nickel, exposed by the opening 372 in the photoresist layer 370 and by the opening 834 in the patterned polymer layer 830, and then electroplating a gold layer with a thickness of between 1 and 20 microns on the nickel layer in the opening 372 in the photoresist layer 370 and/or in the opening 834 in the patterned polymer layer 830.

Next, referring to FIG. 63, the photoresist layer 870 is stripped. Next, referring to FIG. 64, the seed layer 342 not under the metal layer 360 and not under the patterned polymer layer 830 is removed using a dry etching process or a wet etching process. If the seed layer 342 is gold and removed by a wet etching process, the etchant for etching the seed layer 342 is potassium iodide. Thereafter, the adhesion/barrier layer 340 not under the metal layer 360 and not under the patterned polymer layer 830 is removed using a dry etching process or a wet etching process. If the adhesion/barrier layer 340 is a titanium tungsten alloy and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrogen peroxide or hydrofluoric acid if the adhesion/barrier layer 340 is titanium and removed by a wet etching process, the etchant for etching the adhesion/barrier layer 340 is hydrofluoric acid.

Referring to FIG. 64, the above-mentioned metal layer 880 may be used as a metal bump capable of being connected to an external circuitry (not shown), such as a ceramic substrate, a printed circuit board, semiconductor chip for chip-on-chip package, glass substrate for a chip-on-glass (COG) package, flex circuit substrate for a chip-on-film (COF) package, a tape carrier for tape-automated-bonded (TAB) package. In the application for COG, COF or TAB packages, the topmost layer of the metal layer 880 is preferably gold, which can be bonded to a metal layer, preferably of gold, formed on the above-mentioned external circuitry or to a metal layer, preferably of tin-containing material, formed on the above-mentioned external circuitry. Alternatively, an anisotropic conductive film (ACF) can be use to electrically connect the metal layer 880 to the above-mentioned external circuitry, such as glass substrate. In the application for being connected to a ceramic substrate, printed circuit board, or semiconductor chip, the topmost layer of the metal layer 880 is preferably tin-containing material, which can be bonded to a metal layer, preferably of gold, formed on the ceramic substrate, printed circuit board, or semiconductor chip, or to a metal layer, preferably of tin-containing material, formed on the ceramic substrate, printed circuit board, or semiconductor chip.

Alternatively, the metal layer 880 is used as a metal pad for being wirebonded thereto. A gold wire 394 can be bonded to the metal layer 880 using a wirebonding process, as shown in FIG. 65. The elements shown in FIG. 65 having same reference numbers as those shown in FIGS. 1-14, 57-58 and 61-64 indicate similar ones described above in FIGS. 1-14, 57-58 and 61-64.

Alternatively, referring to FIG. 66, if the metal layer 880 includes a solder material, such as tin-lead alloy or a tin-silver alloy, the metal layer 880 after being reflowed may be shaped like a ball. Furthermore, the metal layer 360 may have another metal pad, exposed by another opening 836 in the patterned polymer layer 830, used to be wirebonded thereto. A gold wire 394 can be bonded to the metal layer 360 exposed by another opening 836 in the patterned polymer layer 830 using a wirebonding process. The openings 836 and 834 may be simultaneously formed using a photolithography process. The elements shown in FIG. 66 having same reference numbers as those shown in FIGS. 1-14, 57-58 and 61-64 indicate similar ones described above in FIGS. 1-14, 57-58 and 61-64.

Alternatively, referring to FIG. 67, the above-mentioned metal layer 880 used to be wirebonded thereto or used as a metal bump bonded to an external circuitry may not cover the patterned polymer layer 830 close to the opening 834 therein. Accordingly, the photoresist layer 870 covers the peripheral region of the exposed surface of the metal layer 360 exposed by the opening 834 in the patterned polymer layer 830 and covers the patterned polymer layer 830 close to the opening 834 therein. The above-mentioned ideas in the paragraph can be incorporated into the process shown in FIGS. 61-64. The elements shown in FIG. 67 having same reference numbers as those shown in FIGS. 1-14, 57-58 and 61-64 indicate similar ones described above in FIGS. 1-14, 57-58 and 61-64.

Alternatively, the metal layer 360 close to the metal layer 880 used to be wirebonded thereto or used as a metal bump bonded to an external circuitry may not be covered by the patterned polymer layer 830, as shown in FIG. 68. The elements shown in FIG. 68 having same reference numbers as those shown in FIGS. 1-14, 57-58 and 61-64 indicate similar ones described above in FIGS. 1-14, 57-58 and 61-64.

The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims. 

1-20. (canceled)
 21. A circuit component comprising: a device comprising a glass substrate and a first metal layer under said glass substrate; and a chip under said device, wherein said chip comprises a silicon substrate, a second metal layer over said silicon substrate, wherein said second metal layer comprises a coil, a dielectric layer over said second metal layer and said silicon substrate, and a metal bump over said silicon substrate, wherein said metal bump contacts said first metal layer.
 22. The circuit component of claim 21, wherein said first metal layer comprises gold.
 23. The circuit component of claim 21, wherein said first metal layer comprises tin.
 24. The circuit component of claim 21, wherein said second metal layer comprises copper.
 25. The circuit component of claim 21, wherein said second metal layer comprises a copper layer having a thickness between 1 and 20 micrometers.
 26. The circuit component of claim 21, wherein said metal bump comprises a third metal layer on said second metal layer and a fourth metal layer on said third metal layer.
 27. The circuit component of claim 21, wherein said metal bump comprises copper.
 28. The circuit component of claim 21, wherein said metal bump comprises nickel.
 29. The circuit component of claim 21, wherein said metal bump comprises gold.
 30. The circuit component of claim 21, wherein said metal bump comprises a copper layer having a thickness between 2 and 30 micrometers.
 31. The circuit component of claim 21, wherein said metal bump comprises a third metal layer on said second metal layer and a tin-containing layer on said third metal layer.
 32. The circuit component of claim 21, wherein said dielectric layer comprises a polymer.
 33. The circuit component of claim 21, wherein said chip comprises a polymer layer over said silicon substrate, wherein said second metal layer is further on said polymer layer.
 34. A chip comprising: a silicon substrate; a first coil over said silicon substrate; a dielectric layer over said first coil and said silicon substrate; and a second coil over said dielectric layer, wherein said second coil is vertically over said first coil and connected to said first coil.
 35. The chip of claim 34, wherein said first coil comprises copper.
 36. The chip of claim 34, wherein said first coil comprises a copper layer having a thickness between 1 and 20 micrometers.
 37. The chip of claim 34, wherein said second coil comprises copper.
 38. The chip of claim 34, wherein said second coil comprises a copper layer having a thickness between 1 and 20 micrometers.
 39. The chip of claim 34, wherein said dielectric layer comprises a polymer.
 40. The chip of claim 34 further comprising a polymer layer over said silicon substrate, wherein said first coil is further on said polymer layer.
 41. The chip of claim 34 further comprising a polymer layer over said second coil and said dielectric layer.
 42. The chip of claim 34, wherein said first coil is provided by a patterned circuit layer comprising a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer.
 43. The chip of claim 42, wherein said first metal layer comprises titanium.
 44. The chip of claim 34, wherein said second coil is provided by a patterned circuit layer comprising a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer.
 45. The chip of claim 44, wherein said first metal layer comprises titanium.
 46. A chip comprising: a substrate; a first dielectric layer over said substrate; a patterned circuit layer on said first dielectric layer and over said substrate; a second dielectric layer on said patterned circuit layer and on said first dielectric layer, wherein said patterned circuit layer has a contact point and left and right regions not covered by said second dielectric layer, wherein said contact point is between said left and right regions; and a metal bump on said contact point, wherein said metal bump comprises a copper layer, wherein said metal bump has a left sidewall horizontally spaced apart from a left portion of said second dielectric layer, and said left region is between said left sidewall and said left portion, wherein said metal bump has a right sidewall horizontally spaced apart from a right portion of said second dielectric layer, and said right region is between said right sidewall and said right portion, wherein said second dielectric layer has no portion between said left sidewall and said left portion and between said right sidewall and said right portion.
 47. The chip of claim 46, wherein said copper layer has a height between 2 and 30 micrometers.
 48. The chip of claim 46, wherein said patterned circuit layer comprises a first metal layer and a second metal layer on said first metal layer, wherein said second metal layer has a sidewall not covered by said first metal layer.
 49. The chip of claim 48, wherein said first metal layer comprises titanium.
 50. The chip of claim 48, wherein said first metal layer comprises titanium nitride.
 51. The chip of claim 48, wherein said first metal layer comprises tantalum.
 52. The chip of claim 48, wherein said first metal layer comprises tantalum nitride.
 53. The chip of claim 48, wherein said second metal layer comprises copper.
 54. The chip of claim 46, wherein said second dielectric layer comprises a polymer.
 55. The chip of claim 46, wherein said first dielectric layer comprises a polymer.
 56. The chip of claim 46, wherein said substrate comprises damascene copper. 